VPX549

Description:

VPX549 is a high-performance 6U OpenVPX FPGA SoC board utilizing the Altera Agilex 7 AGIB027 processor. Integrated on-board is a quad Texas Instruments ADC32RF55digitizer array, providing an octal-channel ADC architecture.

The board provides 16 GB of DDR4 memory to the FPGA fabric, configured as two independent 8 GB, 64-bit wide banks with Error Correction Code (ECC). The Hard Processor System (HPS/ARM) is supported by a dedicated single bank of 4 GB, 32-bit wide DDR4 memory with ECC.

The FPGA interfaces directly to the P1 and P2 backplane connectors via 32 high-speed SERDES lanes supporting PCIe, SRIO, Serial Lite II, and multi-rate Ethernet (1G/10G/25G/50G/100G). Additionally, general-purpose I/O (GPIO) signals and LVDS lines are routed directly to the rear transition interface. Two 1000Base-X and two 1000Base-T are routed to the VPX P4 backplane connector.

A front panel 1000BASE-T GbE is provided. The front panel also features 12 status and user-defined LEDs alongside 8x SSMC connectors for the RF analog inputs. Further, the front panel includes a QSFP-DD transceiver which connects to eight FHT transceivers spread across two Agilex 7 F-Tiles. The QSFP-DD can typically support up to 2x 100G Optical Links when the ADC JESD lanes are in use. Auxiliary front-panel GPIO consists of 24 single-ended lines, 8 LVDS transmit (TX) pairs, and 8 LVDS receive (RX) pairs.

An on-board PLL locks onto incoming system clocks to facilitate synchronization with external clock references, distributing phase-synchronized clocks to the ADC array for fully coherent RF sampling across all eight channels. For applications requiring the lowest possible jitter, the on-board PLL can be bypassed by supplying an external input clock up to the maximum sampling frequency.

The VPX549 includes platform health management and monitoring capabilities powered by our field-proven IPMI software, delivering Tier-2 support compliant with VITA 46.11. The unit is available in a range of temperature, shock, and vibration configurations per ANSI/VITA standard.

Designed for open architecture frameworks, the module closely aligns with the following OpenVPX and SOSA aligned slot profile: SLT6-PAY-4F1Q2S2U2T-10.6.4-n

Note: VPX549 omits the P3, P5, and P6 connector allocations.

Key Features:

• 6U VPX form factor compliant to VITA 46.0, VITA 65.0 (Open VPX) and aligned with the Sensor Open Systems ArchitectureTM (SOSA)
• Utilizing Intel Agilex-7 SoC (AGIB027) FPGA with Quad Core ARM Cortex-A53 in 6U VPX form factor
• Quad ADC Texas Instrument (TI) ADC32RF55
  • Octal Channels at 14-bit @ 3 GSPS
• 64 GB of Flash for the file system
• 256 MB Boot Flash
• 4 GB of DDR-4 (32-bit) with ECC to the HPS
• Two banks of 8GB of DDR-4 (64-bit wide) with ECC to the Fabric for total of 16 GB
• QSFP-DD Optical Link with 8 SERDES
  • Configurations such as dual 100GbE or 8x 25GbE
  • Others such as high-speed Serial Lite II, etc.
• Health Management through dedicated Processor per VITA 46.11 Tier-2 support

VPX549 Datasheet