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VPX, OpenVPX and SOSA-aligned ADC / DAC Boards

Our portfolio contains ADC / DAC boards with AMD Xilinx Zynq Ultrascale+ RFSoC or Zynq Ultrascale+ MPSoC as well as Virtex or Kintex Ultrascale+ FPGAs and separate AD / DA converters in 3U and 6U, air-cooled and conduction cooled.

Below you find a selection of available ADC / DAC boards.

Please contact us at vpx@emcomo.de if you have any questions or other requirements.

VPX572

Dual ADC 12-bit @ 6.4 GSPS or Quad ADC @ 3.2 GSPS Virtex UltraScale+, 3U VPX

  • Dual ADC 12-bit @ 6.4 GSPS (ADC12DJ3200) or Quad ADC @ 3.2 GSPS
  • Health Management through dedicated Processor

Datasheet
 
 

VPX555

Virtex and Zynq UltraScale+ FPGAs with High-speed ADC/DAC in 6U VPX

  • Xilinx Virtex UltraScale+ XCVU13P FPGA
  • Xilinx Zynq UltraScale+ XCZU4CG FPGA
  • High speed ADC/DAC utilizing 3x AD9081
  • Synchronized 12 channel DAC/ADC

Datasheet

 

VPX584

Four ADC 12-bit @ 10.25 GSPS with UltraScale+, 3U VPX

  • Four ADC 12-bit @ 10.25 GSPS
  • Utilizing Analog Device AD9213
  • Xilinx UltraScale+ XCVU13P FPGA
  • High speed SERDES to the P1/P2

Datasheet
 

 

 

 

VPX574

Dual RF Agile Transceiver with Front I/O, 3U VPX

  • Dual RF transceiver (AD9364)
  • Xilinx UltraScale+ XCZU15EG FPGA
  • 8 GB of 64-bit wide DDR4 Memory (single bank) with ECC
  • MPSoC with block RAM and UltraRAM

Datasheet

 

 

 

 

 

VPX578

3rd Generation Zynq RFSoC UltraScale+, 6U VPX

  • 3rd Generation Xilinx RFSoC XCZU47DR
  • 8 ADC and 8 DAC simultaneous processing
  • Suitable for 5G/4G/LTE and SDR deployment
  • 8GBytes of DDR-4 with ECC to PS

Datasheet

 

VPX582

Integrated Octal RF Transceiver in for L1/L5 Band or Wider Freq 800MHz to 2.8GHz in 3U VPX

  • Octal RF transceiver utilizing AD9371 and/or AD9375
  • Xilinx UltraScale+ XCZU15EG FPGA
  • 8 GB of 64-bit wide DDR-4 Memory with ECC to ARM
  • 8 GB of 64-bit wide DDR-4 Memory to FPGA

Datasheet

VPX577

Quad ADC 12-bit @ 10.4 GSPS with Dual DAC @ 9 GSPS Virtex UltraScale+, 6U VPX

  • Virtex UltraScale+ with XCVU13P FPGA
  • Two FPGA banking option for how the ADC/DAC are connected to the SLR region (ordering option E)
  • Zynq UlatraScale+ with XCZU4CG
  • Dual bank of DDR-4 memory with 8G per bank

Datasheet
 

VPX587

300 MHz to 6 GHz Octal Versatile Wideband Transceiver (MIMO), Virtex UltraScale+™, 3U VPX

  • Xilinx Virtex UltraScale+™ XCVU13P FPGA
  • Four AD9371s or AD9375s on one module
  • Octo complete transceiver signal chain solution
  • Tx synthesis bandwidth to 250 MHz

Datasheet

 

VPX599

Dual ADC @ 10.4 or 6.4 GSPS and Dual DAC @ 12 GSPS, UltraScale™, 3U VPX

  • 3U FPGA Dual ADC and Dual DAC per VITA 46
  • Xilinx Kintex UltraScale™ XCKU115 FPGA
  • Dual ADC 12-bit @ 10.4/6.4 GSPS or quad ADC @ 5.2/3.2 GSPS with TI ADC12DJ5200 or ADC12DJ3200
  • Option for ADC12DJ5200, ADC12DJ3200 or ADC12DJ2700

Datasheet

 

 

VPX579

3rd Generation Zynq RFSoC UltraScale+, 6U VPX

  • 3rd Generation Xilinx RFSoC XCZU49DR
  • 16 ADC and 16 DAC simultaneous processing
  • Suitable for 5G/4G/LTE and SDR deployment
  • 8GBytes of DDR-4 with ECC to PS

Datasheet