FMC160
Complete FMC Timing Module with IRIG-B, GPS, 1PPS, IEEE1588, SyncE
Description:
FMC160 is an FPGA Mezzanine Module per VITA 57 specification providing a complete timing solution. FMC160 has 1PPS, Sine Wave clock, IRIG-B input, IRIG-B out and a GbE.
The module can take its upstream time/frequency from one of:
- GPS (freq and time + location/velocity/other metadata)
- IEEE1588 PTP (freq and time)
- IRIG-B AM/DCLS/Manchester (freq and time)
- 1PPS (freq only)
- Sine Wave Clock In (freq only)
- Synchronous Ethernet (freq only, can be combined with IEEE1588 PTP)
- Carrier board 1PPS via FMC connector (freq only)
The module can provide its downstream time/frequency to all of:
- IEEE1588 PTP (freq and time)
- IRIG-B AM/DCLS/Manchester (freq and time)
- 1PPS (freq only, can be combined with
- NMEA for freq and time) NMEA (time only, can be combined with 1PPS for freq and time)
- Clock Out (freq only)
- Synchronous Ethernet (freq only)
- Carrier board Host interface and clocks via FMC connector
The standard firmware on FMC160 interfaces to the carrier FPGA through SPI for obtaining time/location/velocity metadata. Additional hardware interfaces are available such as PCIe, Ethernet, Aurora, etc. Contact us if you have an interest in interfacing to the FMC160 via one of these protocols via the FMC connector.
The module has an on board 5x DPLL. The DPLL synchronizes 1Hz to 750MHz, providing frequency with jitter cleaning. Complies with ITU-T G.8286, G.813, G. 812 and Telcordia GR-253/GR-1244. The module will automatically holdover upon loss of reference while still providing its time/frequency outputs to the rest of the system. The DPLL allows for fast lock to 1HZ input taking only 3 to 60 seconds depending on the reference input compared to 10 minutes or more for previous solutions.
The FMC160 provides standard NMEA format via RS-232 for external devices.
The FMC160 provides synchronized clock to the carrier thru its CLK0 and CLK1. The FMC160 has CLK2 and CLK3 routed to the DPLL as an input reference option. The Module also routes from the DPLL to the LA00/LA17 clock pins.
Key Features:
- FPGA Mezzanine Card (FMC) compatible with VITA 57.1
- Single-module complete timing card supporting grandmaster clock / slave clock modes
- GPS receiver on board
- Sine Wave clock input (typically 10MHz)
- 1PPS/IRIG-B DCLS/Manchester input
- Clock/IRIG-B DCLS/Manchester output
- IRIG-B Amplitude Modulated (AM) input
- IRIG-B Amplitude Modulated (AM) output
- Synchronous Ethernet (SyncE) Master/Slave
- IEEE1588 PTP Master/Slave via 10/100/1000Base-T
- NMEA standard serial output from GPS
- Host board interface for optional communication with FMC carrier board host FPGA
- 5x DPLL on board for precise timekeeping
- Carrier board FPGA reference design sources available