FMC235
Quad channel ADC 16-bit @ 250 MSPS, single channel DAC 14-bit 500 @ MSPS
Description:
FMC235 is an FPGA Mezzanine Card (FMC) per VITA 57.1 specification. The board has Quad ADC and single DAC with DC coupled Input and Output.
FMC235 utilizes dual ADS42JB69 ADCs which provides quad ADC 16‑bit conversion at rates of up to 250 MSPS, and a single DAC3171 providing 14-bit conversion at rates of up to 500MSPS.
The analog input, digital output, clock and trigger interfaces of the FMC235 are routed via SSMC connectors. The internal clock frequency is programmable and the clock is capable of locking to an external reference.
Key Features:
- FPGA Mezzanine Card (FMC) per VITA 57
- Dual ADS42JB69 (Quad ADC in total), 16-bit @ 250MSPS
- JESD204B lanes from each ADC
- Single DAC3171 (LVDS Based), 14-bit @ 500MSPS
- Front end RF is DC coupled for the ADC and the DAC
- Excellent dynamic performance
- Front panel interface includes CLK In, Trig In and Trig Out